1. Field of the Invention
The present invention relates to adiabatic logic circuits.
2. Description of the Prior Art
Adiabatic logic circuits are described in particular in chapter 6 of a work by C. Piguet, whose title is xe2x80x9cCircuits complexesxe2x80x94Evolution de la technologie VLSIxe2x80x9d, derived from courses on complex circuits given at the Ecole Polytechnique Fxc3xa9dxc3xa9rale de Lausanne, Switzerland, 1998, and in an article by L. J. Svensson et al. entitled xe2x80x9cDriving a capacitive load without dissipating fCV2xe2x80x9d, IEEE Symposium on Lower Power Electronics, pp. 100 and 101, 1994.
The above circuits have the advantage of reducing consumption in accordance with the equation:   E  =            τ      T        ⁢          CV      dd      2      
in which xcfx84 is a delay internal to the circuit, C is the internal capacitance, T is the rise time of the clock signal, which also provides the power supply, and Vdd is the potential of one of the logic levels that the input and output variables of the circuit can take.
For an adiabatic logic circuit to operate the input variables which are applied to it must reach their stable logic level before the clock signal changes state. This is a difficult problem if several adiabatic logic circuits are connected in cascade, the output of one circuit then constituting one of the input variables of a subsequent gate. The clock signal of a second circuit must then not change state before the output signal of the preceding circuit has stabilized. It is therefore necessary to use interleaved clock signals from what is usually referred to as a xe2x80x9cretractile cascade clockxe2x80x9d. Because the input signals are generally in the true form and in the complemented form, and must be valid before the clock signal rises, the adiabatic circuit must be able to deliver its output signal both in the true form and in the complemented form.
FIG. 1 of the accompanying drawings illustrates this concept. The adiabatic logic circuits C1, C2 and C3 in the figure are connected in cascade and their respective clocks xcfx861, xcfx862 and xcfx863 are retractile clocks, as shown by the signals represented in FIG. 1.
A clock generator able to generate this type of clock signal is complex and difficult to design, especially if the xe2x80x9clogic depthxe2x80x9d is great, i.e. if many logic circuits are connected in cascade.
However, some circuits include only two logic gates in series, such as programmable logic arrays (PLA) and read-only memories (ROM); this corresponds to a xe2x80x9clogic depthxe2x80x9d equal to 2 and therefore requires only two clock signals.
The object of the invention is to provide an adiabatic logic circuit which uses a precharging mechanism to reduce the number of transistors needed.
The invention therefore provides an adiabatic logic circuit including bidirectional transfer members to which input variables of the circuit are applied and which are connected between a first circuit terminal adapted to be connected to a clock generator whose clock signal also powers the circuit and a second circuit terminal forming its output and adapted to assume two logic levels as a function of the input variables, the circuit also including a third terminal connected to the second terminal via the inherent capacitance thereof and means for precharging the second terminal to a potential corresponding to one of the logic levels outside active phases of the clock signal.
According to other features of the invention:
the precharging means include a transistor whose source-drain path is connected between the second terminal and the potential of one of the logic levels and the transistor is connected to a precharging signal generator,
the transistor is an n-channel transistor and the logic level is the potential Vss of the circuit,
the transistor is a p-channel transistor and the logic level is the potential Vdd of the circuit,
the bidirectional transfer members are connected in series,
the bidirectional transfer members are connected in parallel.
The invention also provides an addressable memory circuit including a matrix of rows and columns and at least one address decoder connected to the rows and including a plurality of adiabatic logic circuits as defined above to which address variables for the memory circuit are applied and wherein the precharging means of the adiabatic logic circuits of the decoder are adapted to receive the same precharging signal.
According to other features of the invention:
the memory circuit includes first and second address decoders whose adiabatic logic circuits are respectively connected to the rows to supply them both the true value of each address and the complement of each address value,
the precharging means of the logic circuits of the decoders are adapted to precharge the second terminal of the logic circuit of which they are part to the potential of the same logic level,
the precharging means of the logic circuit of one of the decoders are adapted to precharge the second terminals thereof to a logic level different than that to which the second terminals of the logic circuits of the other decoder are precharged,
the memory circuit further includes an output network connected to the columns and including a plurality of adiabatic logic circuits as defined above and wherein the precharging means of the logic circuits of the output network are adapted to receive the same precharging signal as the precharging means of the logic circuits of at least one decoder, or possibly the precharging signal extended,
the output network includes a logic circuit for each of the columns and the transfer members of the circuits are at crossings of the rows and the columns of the matrix at which a logic xe2x80x9c1xe2x80x9d must be present, and
the output network forms a multiplexer.
Other features and advantages of the invention will become apparent in the course of the following description, which is given by way of example only and with reference to the accompanying drawings.